Design For Testability

Who can benefit from this Course:

• M-tech / B-tech Students.
• Entry-level DFT engineers, who want to learn DFT in a systematic way from fundamentals to techniques.
• Application Engineers who need to understand DFT, for effective customer interactions & problem-solving.
• Working Professionals from the VLSI industry, currently working in other areas such as RTL Design, FPGA Design, Synthesis, STA, board-level testing, etc., and aspire to change to DFT career.
• Faculties from Engineering Colleges across India.
• Professionals from Electrical and electronics engineering background with good academic Percentage but are working in other industries, and who are desiring to make a career in VLSI.
• Working professionals from Embedded background working in PCB designing, assembling, DSP, testing, RFIDs, etc.,

“Best VLSI Training Institutes in Bangalore”

Pre-requisites:

● Working knowledge of Linux.
● Knowledge of Digital Electronics fundamentals.
● Knowledge of Verilog and the ability to design circuits using Verilog.
● Knowledge of CMOS Fundamentals and ASIC / SOC flow is an added advantage to understand the concepts.

• Introduction
• Scan Architecture
• Inputs and outputs
• DRC checks
• Scan Insertion
• Scan Types
• Scan Styles
• Lock up Latches Insertion
• Summary

• Introduction
• ATPG Algorithm
• Inputs and outputs
• ATPG fault models

stuckat
transition
path delay
bridging

• DRC
• Fault classes
• Scan compression pattern generation.
• Test coverage and fault coverage
• Coverage analysis
• Summary

• Introduction
• MBIST Architecture and flow
• Inputs and outputs
• Need of MBIST
• Advantage and disadvantage of MBIST
• MBIST Algorithms
• Types of memory testing
• Memory Fault types
• Memory Repair
• Summary