Design For Testability

Start Date

16 Jan 2021


3 Months Training + 2 Months Internship

Training Type

Weekend Online Class


Hands-on Labs

GOLDENLIGHT SOLUTIONS DFT course designed and delivered by working professionals from Semi -Conductor Industry, and as per its current trending requirements is intended for engineers who are seeking to learn DFT concepts and methodologies to effectively carry out their jobs and help in success of the chip.

Special emphasize on Fundamentals, Application of Concepts and On job training, with minimum of 50 – 60 % time for lab sessions.

Weekend: 10 Weeks
Full Time: 6 Months Course + 6 Months Paid Internship

Training Delivery Model:

• Interactive Live Online Sessions.
• Lab access through VPN.


GLS Certified DFT Course completion certificate to be awarded to all participants who successfully complete our tests and evaluation process.

Who can benefit from this Course:

• M-tech / B-tech Students.
• Entry-level DFT engineers, who want to learn DFT in a systematic way from fundamentals to techniques.
• Application Engineers who need to understand DFT, for effective customer interactions & problem-solving.
• Working Professionals from the VLSI industry, currently working in other areas such as RTL Design, FPGA Design, Synthesis, STA, board-level testing, etc., and aspire to change to DFT career.
• Faculties from Engineering Colleges across India.
• Professionals from Electrical and electronics engineering background with good academic Percentage but are working in other industries, and who are desiring to make a career in VLSI.
• Working professionals from Embedded background working in PCB designing, assembling, DSP, testing, RFIDs, etc.,


● Working knowledge of Linux.
● Knowledge of Digital Electronics fundamentals.
● Knowledge of Verilog and the ability to design circuits using Verilog.
● Knowledge of CMOS Fundamentals and ASIC / SOC flow is an added advantage to understand the concepts.

DFT Program Modules

Module 1 : Digital Fundamentals

  • MOS Concepts
  • Combinational Logic
  • Sequential Logic
  • Counters, Sequence Detectors, State Machines
  • Timing Aspects

Module 3 : DFT Fundamentals

Test Bench (TB) Development

  • Introduction to DFT
  • Need of DFT
  • DFT flow in SOC
  • DFT Architecture
  • DFT Methods
  • DFT Approach
  • OCC Architecture
  • Summary

Module 5 : Compression

  • Introduction
  • Why compression
  • Compression Architecture
  • Compression ratio
  • Compression mode and bypass mode
  • Inputs and outputs
  • DRC
  • Masking logic
  • Summary

Module 7 : Simulation

  • Introduction
  • Types of Simulation
  • Serial and parallel simulation
  • Difference between serial and parallel simulation Inputs and outputs
  • Inputs and outputs
  • Simulation Mismatches.
  • Summary

Module 4 : Scan Insertion

  • Introduction
  • Scan Architecture
  • Inputs and outputs
  • DRC checks
  • Scan Insertion
  • Scan Types
  • Scan Styles
  • Lock up Latches Insertion
  • Summary

Module 6 : ATPG

  • Introduction
  • ATPG Algorithm
  • Inputs and outputs
  • ATPG fault models
  • stuckat
    path delay

  • DRC
  • Fault classes
  • Scan compression pattern generation.
  • Test coverage and fault coverage
  • Coverage analysis
  • Summary

Module 8 : MBIST

  • Introduction
  • MBIST Architecture and flow
  • Inputs and outputs
  • Need of MBIST
  • Advantage and disadvantage of MBIST
  • MBIST Algorithms
  • Types of memory testing
  • Memory Fault types
  • Memory Repair
  • Summary


Ready to get started?

Get in touch


Kasturi Plaza
3rd Floor, # 3M-409, 3rd Main Road,
Outer Ring Road, NGEF Layout,
Kasturi Nagar, Bengaluru – 560043

Contact No:




4th Cross Rd, HAL 3rd Stage
Kodihalli, Bengaluru,
Karnataka 560008

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