Synthesis and Static Time Analysis

STA course is designed for the working VLSI engineers who want to learn/enhance their knowledge on Synthesis and Static Timing Analysis (STA).

The course will be delivered by experts in STA, who have worked on multiple tape-outs for timing closure. Special emphasize on Fundamentals, Application of Concepts and on the job training, with a minimum of 50 – 60 % time for lab sessions

Course Details

Duration:

Weekend: 5 Weeks

Training Delivery Model:

• Interactive Live Online Sessions.

• Lab access through VPN.

Certification:

GLS Certified STA Course completion certificate to be awarded to all participants who successfully complete our tests and evaluation process.

Who can benefit from this Course:

  • M.Tech / B.Tech Students. • Working Professionals from the VLSI industry, currently working in some areas (RTL Design, Verification, FPGA Design, DFT, Physical design, Low Power PD) who want to learn Synthesis & STA thoroughly.
  • Synthesis, STA Engineers who want to fill the gaps in their understanding & strengthen STA knowledge to deliver effectively in the current role.
  • CAD / Methodology Engineers or Application Engineers who have come across Synthesis & STA in their work, but don’t have a good understanding of its working.
  • Any working VLSI Engineer seeking to learn Synthesis & STA.
  • Faculties from Engineering Colleges across India.
  • Professionals from Electrical and electronics engineering background with good academic Percentage but are working in other industries, and who are desiring to make a career in VLSI.
  • Working professionals from Embedded background working in PCB designing, assembling, DSP, testing, RFIDs, etc.,

Pre-requisites:

  • Working knowledge of Linux.
  • Knowledge of Digital Electronics fundamentals.
  • Knowledge of Verilog and the ability to design circuits using Verilog.
  • Knowledge of CMOS Fundamentals and ASIC / SOC flow is an added advantage to understand the concepts.
Module 1 : Synthesis
  • Introduction to Synthesis and its flow
  • Constraining Design for timing, area & power
  • Understanding & Exploring .lib
  • Synthesizing the Design
  • Checks on Timing
  • Reports, Analysis and Debugging of results
  • Optimization Techniques
  • Low Power Synthesis using UPF
Module 2 : Static Timing Analysis
  • Fundamentals of STA
  • Delays & Libraries
  • Constraining design using SDC commands
  • Clock generations, Handling Clocks and Cock exceptions
  • Timing Exceptions
  • Post Layout STA using SPEF
  • Multi-Mode, Multi-Corner STA
  • Cross talk & Noise Analysis
  • Timing ECOs generation, What-If Analysis
  • Timing Challenges

OUR FACILITY

Ready to get started?

Get in touch

Bangalore

2nd Floor, Workflo Durgawaves,
B.Narayanapura, Mahadevapura
Outer Ring Road, Bangalore
Karnataka- 560016

Bangalore

4th Cross Rd, HAL 3rd Stage
Kodihalli, Bengaluru,
Karnataka 560008

Hyderbad

Lodha Meridian
High-tech city Road
KPHB Hyderabad

×
Register for GLV VLSI Universe Drop a Query Become our Trainer