In digital circuit design, Register-Transfer Level (RTL) is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those signals.
RTL abstraction is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations of a circuit, from which lower-level representations and ultimately actual wiring can be derived. Design at the RTL level is typical practice in modern digital design.
Unlike in software compiler design when register-transfer level intermediate representation is the lowest level, RTL level is the usual input that circuit designers operate on and there are many more levels than it. In fact, in circuit synthesis, an intermediate language between the input register transfer level representation and the target netlist is sometimes used. Unlike in netlist, constructs such as cells, functions, and multi-bit registers are available. Examples include FIRRTL and RTLIL.
Weekend: 12 weeks
Full Time: 6 Months Course + 6 Months Paid Internship
Next Batch: MMM – YYYY
Training Delivery Model:
- Interactive Live Online Sessions
- Lab access through VPN Secure connection 24/7, till the End of Class
- Brush-up Classes: Wed, Thu, and Fri of Every Week.
GLS Certified RTL Course completion certificate to be awarded to all participants who successfully complete our tests and evaluation process.
This is the Chance, Don’t Miss the Opportunity.
- ₹ xx,xxx.xx/- + GST (18%)
- Confirm your program enrollment by making payment of ₹ 5,000/- to below given account details.
- Remaining Fee payment can be paid in 2 installment with gap period of one and half month.
Who can benefit from this Course:
- M.Tech / B.Tech Students.
- Working Professionals from the VLSI industry, currently working in some areas (RTL Design, Verification, FPGA Design, DFT, Physical design, Low Power PD) who want to learn Synthesis & STA thoroughly.
- Synthesis, STA Engineers who want to fill the gaps in their understanding & strengthen STA knowledge to deliver effectively in the current role.
- CAD / Methodology Engineers or Application Engineers who have come across Synthesis & STA in their work, but don’t have a good understanding of its working.
- Any working VLSI Engineer seeking to learn Synthesis & STA.
- Faculties from Engineering Colleges across India.
- Professionals from Electrical and electronics engineering background with good academic Percentage but are working in other industries, and who are desiring to make a career in VLSI.
- Working professionals from Embedded background working in PCB designing, assembling, DSP, testing, RFIDs, etc.,
- Working knowledge of Linux.
- Knowledge of Digital Electronics fundamentals.
- Knowledge of Verilog and the ability to design circuits using Verilog.
- Knowledge of CMOS Fundamentals and ASIC / SOC flow is an added advantage to understand the concepts.
- Main Trainer, best in Industry, with experience of 15+ Years and on going projects
- You will also have Associate Trainer, having experience of 10+ Years
- Associate train to help you throughout the program to clear your doubts.
- INDIVIDUAL ATTENTION
- Top most used in Industry
- Synopsys / Mentor
- Student Loan available
- EMI available
- Get Loan, confirming your program enrollment by making payment of ₹ 5,000/- to below given account details.
- Linux Basics
- VLSI Design Flow
- Advanced Digital Design
- RTL Integration
- RTL Synthesis
- Hands on Projects
- File & Directory Management
- User Administration
- Environment Variables
- Commonly used commands
- RTL coding, lint checks
- RTL integration
- Connectivity checks
- Functional Verification
- Synthesis & STA
- Gate level simulations
- Power aware simulations
- Placement and Routing
- Custom Layout
- Post silicon validation
- Digital Design basics
- Combinational logic
- Sequential logic, FF, latch, counters
- Setup time, Hold time, timing closure, fixing setup time and hold time violations
- STA basic concepts time, Hold time, timing closure, fixing setup time and hold time violations
- Detailed overview of all Verilog-2001 constructs
- Multiple hands on projects
- Pattern detector
- Synchronous and Asynchronous FIFO
- Interrupt controller
- SPI Controller
- Watchdog timer
- PISO and SIPO
- Vending Machine
- Overview of RTL Integration
- Manual RTL integration
- Need for Tool based Integration
- Core Tools Basics
- Usage model for IP packaging
- Introduction of Synthesis
- Data Setup of DC
- Accessing Design and Library Objects
- Constraints: Reg-to-Reg and I/O Timing
- Constraints: Input Transition and Output Loading
- Constraints: Multiple Clocks and Exceptions
- Constraints: Complex Design Considerations
- Post-Synthesis Output Data
- 3 Hands on Projects based on complete RTL integration flow, CDC, Lint, Synthesis and STA
Ready to get started?
Get in touch