Design Verification  

GLS ASIC DV course designed and delivered by working professionals from Semi-Conductor Industry, and as per its current trending requirements. Special emphasis on Fundamentals, Application of Concepts and on the job training, with a minimum of 50 – 60 % time for lab sessions

Course Details

Duration:
Weekend: 15 weeks
Full Time: 6 Months Course + 6 Months Paid Internship

Training Delivery Model:

Online / Classroom

Certification:

GLS Certified DV Professional Course completion certificate to be awarded to all participants who successfully complete our tests and evaluation process.

Who can benefit from this Course:

• M.Tech / B.Tech Students.
• Working Professionals from the VLSI industry, currently working in other areas such as RTL Design, FPGA Design, Synthesis, STA, board-level testing, etc., and aspire to change to ASIC Design Verification career.
• Faculties from Engineering Colleges across India.
• Professionals from Electrical and electronics engineering background with good academic Percentage but are working in other industries, and who are desiring to make a career in VLSI.

Pre-requisites:

● Working knowledge of Linux.
● Knowledge of Digital Electronics fundamentals.
● Knowledge of Verilog and the ability to design circuits using Verilog.

Module 1 : Digital Fundamentals

  • MOS Concepts
  • Combinational Logic
  • Sequential Logic
  • Counters, Sequence Detectors, State Machines
  • Timing Aspects

Module 2 : Basics of Linux and Perl Introduction to Digital Design and Verification using System Verilog and Verilog

  • Data Types
  • Arrays
  • Procedural Statements & Control Flow
  • Placement, STA
  • Processes
  • Tasks & Functions
  • Classes
  • Randomization & Constraints
  • Inter Process Communication
  • Assertion
  • Coverage

Module 3 : Advanced Verification

Test Bench (TB) Development

  • Linear TB
  • File IO TB
  • State Machine based TB
  • Task based TB
  • Self-Checking TB
  • Bus Functional Model
  • Driver
  • Protocol Monitor
  • Score Board
  • Functional Coverage

Verification Flow

  • Planning Verification Environment Architecture
  • Feature Extraction from Specification

Direct Programming Interface (DPI)

Mini Project (Using Bus Interface)

Module 4 : Universal Verification Method

UVM Structure for a UVC

  • Introduction
  • UVM TB
  • UVM Sequence
  • UVM Configuration
  • UVM Phases
  • UVM Driver
  • UVM Monitor
  • UVM Scoreboard
  • UVM Environment
  • UVM Test
  • UVM TB top with example

UVM Structure for a UVC

  • UVM callback
  • UVM Events
  • UVM TLM
  • UVM Barrier
  • UVM Heartbeat

Mini Project

  • AHB UVC
  • Module 5 : Additional Advanced Topics

    • Gate Level Simulation
    • Power Simulation
    • Assertion Based Verification
    • H/W-S/W Co-simulation
    • Functional Safety (Fault Injection)
    • Formal Verification
    • Regression
    • AMS Modeling
    • Perspec System Verifier

    OUR FACILITY

    Ready to get started?

    Get in touch

    Bangalore

    AMBIKA CORNER
    3rd floor, 3rd Cross Rd,
    East of NGEF Layout, Kasturi Nagar,
    Bengaluru, Karnataka 560043.

    Contact No:

    +91-98867-09385

    Email:

    info@goldenlightsolutions.com

    Bangalore

    4th Cross Rd, HAL 3rd Stage
    Kodihalli, Bengaluru,
    Karnataka 560008

    ×
    Register for GLV VLSI Universe Drop a Query Become our Trainer