Careers

• 6 – 8 years of experience in Verification
• Have done 2-3 Top level SoC verification
• Lead a team of Engineers
• Expertise with AXI/AHB/APB protocols
• Knowledge/Expertise with PCIe/MIPI will be an added advantage
• Knowledge with processor verification is a plus
• Extensive knowledge of SystemVerilog and verification methodologies particularly OVM/UVM
• Strong experience in the implementation of verification infrastructures, test benches, models, assertions
• Expertise with development of constrained random tests scenarios
• Running regression tests and analysis of results including functional coverage
• Hands on with RTL/Gate Level Simulation
• Expertise with industry standard tools like VCS/Verdi/NCSim/Questa etc.
• Scripting skills with PERL/TCL
• Should possess good Leadership Skills
• Must have good communication & problem-solving skills.
• Should be with Go-getter attitude
• Mentor Team Members
• Bachelor/Master Degree in Electronics Engineering

Job Location: Bangalore Designation: Lead Design Verification Engineer Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics Number of Positions: 4

• 3 to 5 years of experience in PnR
• Have in-depth knowledge of entire physical design process from RTL to GDS2 generation which includes floorplan, Placement, CTS, Routing
• Have hands-on experience in latest sub-micron technologies below 20nm
• Have done good number of Block level PnR with Timing Closure
• Familiar with Physical Verification flows (DRC/LVS/EM/IR)
• Experience in ECO implementation
• Familiarity with any of Scripting languages –PERL, TCL
• Should be a quick learner and have good attention to detail
• Must have good communication & problem-solving skills.

Job Location: Bangalore/US Designation: Senior Physical Design Engineer Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics Number of Positions: 40

• Expertise with AXI/AHB/APB protocols
• Knowledge/Expertise with PCIe/MIPI will be an added advantage
• Knowledge with processor verification is a plus
• Extensive knowledge of System Verilog and verification methodologies particularly OVM/UVM
• Strong experience in the implementation of verification infrastructures, test benches, models, assertions
• Expertise with development of constrained random tests scenarios
• Running regression tests and analysis of results including functional coverage
• Hands on with RTL/Gate Level Simulation
• Expertise with industry standard tools like VCS/Verdi/NCSim/Questa etc.
• Scripting skills with PERL/TCL
• With Excellent communication and interpersonal skills
• Very good team player, self motivated and creative in problem solving

Job Location: US Designation: Senior Verification Engineer Experience: 3+ years to 8 years Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics Number of Positions: 15

• Minimum 3 years of experience in areas of SOC-DFT Implementation and Integration
• Hands-on experience and knowledge of ATPG, ATPG-DRC clean-up, Pattern
• Generation, fault models, coverage analysis and improvement
• Hands-on experience with pattern generation for various fault models, Stuck-At, TDF, PDF, IDDQ
• Experience with pattern verification, simulation debug, ATE pattern delivery and silicon bring-up
• Experience with one or more scan/ATPG solutions with Tessent Scan, FastScan, TestKompress
• Synopsys DC, DFTC, DFTMAX, Tetramax
• Experience with pattern verification and debug VCS, Simvision, NC-verilog, Questa
• Desired experience with failure diagnostics, silicon debug and interfacing with ATE and test engineers for bring-up
• Preferred but not required MBIST implementation and experience with MBIST pattern generation and verification
• Preferred but not required experience with one or more MBIST solutions Tessent
• BIST, MBIST Architect, SMS
• Experience with shell scripting, Verilog, Tcl and/or Perl/Python
• Strongly desired understanding of IEEE 1149.1, P1500 and Core-Based Testing Standards
• Desired experience with coverage improvement and yield improvement
• Desired experience with test constraint generation and working with STA for test mode timing closures
• Desired familiarity with DFX concepts
• With Excellent communication and interpersonal skills
• Very good team player, self-motivated and creative in problem solving

Job Location: Bangalore/Hyderabad/US Designation: Senior DFT Engineer Experience: 4+ years Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics Number of Positions: 5

Roles & Responsibilities

• Well versed in Verilog and SV with good understanding of RTL design, verification and synthesis practices. Prior work experience in the RTL and/or gate level verification domain is a must.
• Well conversant with different verification methodologies like assertion, function and test coverage with good understanding of test generation process.
• Knowledge on low power design and verification methods using UPF is a must.
• Expertise in RTL quality sign-off through lint checks, IP to SoC integration, IP hand-off, constraints etc., RTL hand-off to backend.
• An expert user of one or more of the following verification tools: NC-Sim*, Modelsim*, VCS, Specman*, Debussy* and/or Verdi*
• Good automation skills in PERL and/or TCL and/or Shell*. Good communication skills (written and verbal).

Job Location: Bangalore/Hyderabad
Designation: Front End RTL Design Automation Engineer
Experience: 2+ years & above
Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics
Number of Positions: 5

• Experience level: 5+ Years.
• Work Experience in Synthesis Constraints development, LINT checks, CDC checks
• Experience in working/leading full-chip STA closure, defining mode requirements and corners for timing closure.
• Experience in Formal Verification with Synopsys Formality and / or Cadence Conformal LEC.
• Chip-level constraint development and constraint validation.
• Strong knowledge of clock tree synthesis, SI analysis.
• Strong understanding of ECO cycle.

Job Location: Bangalore/Hyderabad/US Designation: Senior Synthesis/STA Engineer Experience: 4+ years Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics Number of Positions: 5

• Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context.
• Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies
• Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space.
• Good handle on IR/EM related issues in memory layouts.
• Must have worked on cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks.
• Strong knowledge of ultra-deep sub-micron layout design related challenges and good understanding of DFM guidelines.
• Experience & or strong interest in memory compilers developed.
• Excellent and demonstrated team player with ability to work with external customers and in cross functional teams.

Job Location: Bangalore Designation: Memory Layout Design Engineer Experience: 3+ Years & Above Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics Number of Positions: 3

As a Verification Engineer / Senior Verification Engineer, you will work with a highly innovative and motivated verification development team using state of the art verification technologies to verify the most advanced DRAM products. The verification infrastructure you develop/implement will be used world-wide by multiple teams to verify DRAM products. You will work closely with Micron’s various design and verification teams all over the world to contribute to the success of the design projects by applying verification tools and techniques, providing verification status and summaries as needed.

Job Responsibilities

• Using advanced verification languages (HVL) and techniques to build a cutting-edge verification platform to fully evaluate memory designs at chip or block level on functionality
• Participating in creating full chip behaviour model that is distributed to Micron’s world-wide external customer’s months before silicon is available
• Building a verification plan, incorporating directed and random patterns that cover all features
• Understanding the functionality and timing requirements of the design
• Understand internal and external datasheets
• Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design

Job Requirements

• 4+ years of experience in Verification
• Solid understanding of Verilog, System Verilog and object-oriented programming
• Experience in VIP development using UVM (or equivalent) is a must
• Good debugging and problem-solving skills are a must
• Experience defining coverage strategy and writing coverage model is a must
• Experience in simulator tools like Synopsys, Cadence, Mentor Graphics is preferred
• Experience in scripting language like Shell, Perl, Python is preferred
• Must possess good communication skills to convey complex technical concepts and ability to work well in a team
• Previous work experience in DRAM memory related fields is a plus

Job Location: Hyderabad/US Designation: Senior Verification Engineer Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics Number of Positions: 5

• 3+ years of experience in AMS/RF layout-design (7nm)
• Good Understanding of CMOS Fundamentals, IC-Fabrication & Circuit-basics
• Good Understanding of Layout-Flow & various Reliability Issues
• Preferred experience in modules like PLL, Data-Converters & PMIC blocks
• Good exposure to EDA tools like Virtuoso LE/XL, Assura, PVS, Calibre
• Preferred experience in Deep Sub-Micron/Finfet / Bi-CMOS technologies
• Independently execute layout-design of the assigned Analog & Mixed-Signal / RF blocks either at Onsite or Off-shore, which includes floor-planning as per area & top-level, parasitic-aware routing & doing various required physical verifications.
• Responsible for the on-time delivery of block-level layouts, with acceptable quality
• Co-ordinate effectively with the customer & team-members, for the successful overall project execution
• Guide junior team-members in their execution of block-level layouts & review their work
• Contribute to effective project-management.

Job Location: Bangalore Designation: Analog Layout Design Engineer Experience: 3+ Years & Above Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics Number of Positions: 5

• Familiar and rich experience with SNPS EDA tools for RTL2GATE flow, i.e. DCT, Primetime, formality
• Solid knowledge at FEINT technologies, i.e. synthesis, formality check, CDC, low-power design flow, and STA analysis
• Good communication skills.
• Good English capability on both writing and speaking
• Good self-learning capability and team-work spirit
• Backend design knowledge is plus

Keywords：SNPS EDA tools for RTL2GATE flow, i.e. DCT, Primetime, forma lity FEINT Complex，STA, synthesis, timing, ECO, LINT, CDC Job Location: China/US Designation: STA Engineer Notice Period: Immediate or Maximum 1 Month Experience: 3+ years Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics Number of Positions: 5

• BS in EE, MS preferred., with minimal 3 years working experience on DFT
• Familiar with DFT tools like TestKompress, FastScan, Tetra max, MBISTarchitect, BSDarchitect etc.
• Should have strong problem-solving skills – Good English hearing, speaking, reading and writing capabilities
• Good team working spirit

Keywords: Cadence DFT architect ATPG MBIST SCAN Job Location: China/US Designation: DFT Engineer Notice Period: Immediate or Maximum 1 Month Experience: 3+ years Number of Positions: 5

• 3 to 5 years of experience in PnR
• Have in-depth knowledge of entire physical design process from RTL to GDS2 generation which includes floorplan, Placement, CTS, Routing
• Have hands-on experience in latest sub-micron technologies below 20nm
• Have done good number of Block level PnR with Timing Closure
• Familiar with Physical Verification flows (DRC/LVS/EM/IR)
• Experience in ECO implementation
• Familiarity with any of Scripting languages –PERL, TCL
• Should be a quick learner and have good attention to detail
• Must have good communication & problem-solving skills.

Keywords：SNPS EDA tools for RTL2GATE flow, i.e. DCT, Primetime, forma lity FEINT Complex，STA, synthesis, timing, ECO, LINT, CDC Job Location: Japan/China/Europe/US Designation: Senior Physical Design Engineer Qualification: Bachelor/Master’s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics Number of Positions: 5

• Responsible for managing SEO and digital ad channels in particular for performance marketing
• Create, execute and optimize campaigns end-to-end Innovate, come up with new campaign ideas and share it with other team members Work with the design and content teams to develop best-in-class marketing campaigns optimized for conversion, relevance and customer preferences Create & drive strategy with the right prioritization of initiatives to deliver the highest returns on marketing spends
• Continuously track and measure campaign level, ad-set level, and ad level performance and come up with actionable insights Drive and track KPIs like revenue, conversions, CPA, CPI, etc. on daily basis and prepare performance reports Acquire insights in online marketing trends in the industry, best practices and keep strategies up-to-date
• Collaborate with internal stakeholders on campaign production schedules, modify activity and notify stakeholders of relevant outcomes, fluctuations, and plans
• Good knowledge in designing using tools like Photoshop and 3D Max

No. of Openings: 4 Requirements

• 2-3 years of experience in SEO and paid campaign management

Bachelor’s Degree

• Excellent analytical skills
• Good communication & interpersonal skills
• Creative outlook and an eye for detail
• Ability to multi-task, work in a fast-paced start-up environment, and get-things-done.

• Provide assistance in general administrative activities
• Assists guests with international calls and directory queries
• Maintains a clean work environment
• Maintains detailed knowledge on the Emergency Response Team and workings of the telephone room in this regard
• Coordinate with facility team for event ma.nagement
• Assist in the allocation and utilization of conference rooms including set and cleaning aspects
• Co-ordinating with the caterer and Admin for Ordering Breakfast, working lunch and snacks for Client/Internal meeting
• Greet and assist guests and ensure all arrangements with respect to their transport, hotel, meeting rooms etc.are fulfilled
• Participate in Emergency Evacuation procedures including crisis management and business continuity
• Assist the team with data input of routine reports and filing
• Process all incoming and outgoing calls accurately and courteously
• Ensure maintaining highest levels of confidentiality with the information accessible
• Strictly abides by standards policies and procedures governing cases of emergency such as fire, bomb scare, and other critical situations
• Sort the incoming and outgoing mails at inquiry box and distribute to the concerned department

Education: Bachelor’s Degree Skills:

• Is able to prioritize tasks and see tight timelines as a challenge
• Ability to demonstrate the skills and activities mentioned above
• Is meticulous and has an eye for details
• Excellent personal presentation and communication skills
• Proficient in the use of Front Office System
• Has excellent interpersonal and communication skills
• Able to read and write English
• Communication skills are utilized a significant amount of time when interacting with others; demonstrated ability to interact with customers, employees and third parties that reflects highly on the hotel, the brand, and the Company
• Ability to see and hear in order to observe and detect signs of emergency situations
• Is able to work on a rotating roster

• • Develop and manage excellent working partnerships with alliance partners and intermediaries relevant to your marketplace and services
  • Develop and implement an annual plan for the growth and development for the commercial and experiential business
  • Provide accurate information/reports to Head of Sales and Retail within agreed time scales
  • Performs all sales-related activities as per Hempel E-Convention and ISO procedures
  • Schedule and run periodic sales and performance review meetings
  • Manage the Vending and Telecommunications Business
  • Keep up to date with the customer and competitive intelligence

Roles & Responsibilities

• • Good team player
  • To grow revenue by developing new Commercial Business opportunities across different revenue streams and to manage ongoing relationships with existing commercial business
  • Promotes and sell Decorative Coatings to the existing customers and new customers
  • Generate business from campaigns and sales plans in new accounts, building a foundation to scale these into larger downstream engagements
  • Build on key relationships to build long term business opportunities
  • Assess business opportunities in terms of risks and benefits and their alignment with center groups long term alignment
  • Prepares Monthly Sales Reports and customer activity and updating on sales activities utilizing CRM.

Education:

• Bachelor’s Degree

No. of Openings:

• 4

Job Description:

• • • Develop and manage excellent working partnerships with alliance partners and intermediaries relevant to your marketplace and services
    • Develop and implement an annual plan for the growth and development for the commercial and experiential business
    • Provide accurate information/reports to Head of Sales and Retail within agreed time scales
    • Performs all sales-related activities as per Hempel E-Convention and ISO procedures
    • Schedule and run periodic sales and performance review meetings
    • Manage the Vending and Telecommunications Business
    • Keep up to date with the customer and competitive intelligence

Roles & Responsibilities

• • • Consistently offer professional, friendly and engaging service
    • Personally greeting all internal/external guests, offering support and directing inquiries
    • Order and maintain office supplies and sales gift inventories
    • Support the EVP of Retail and Director of Sales and Marketing in day to day activities including VIP arrivals, scheduling of appointments for the day and email correspondence
    • Answer phones adhering to Fairmont telephone etiquette standards, return calls and deliver messages in a timely manner
    • Data entry and production of reports as requested by EVP of Retail and Director of Sales and Marketing
    • Prioritize all telephone calls, in-person visitors and schedule appointments

Education:

• Bachelor’s Degree

No. of Openings:

• 4