Analog Layout Design 

GLS Analog Layout Design course designed and delivered by working professionals from Semi-Conductor Industry, and as per its current trending requirements using industry-standard EDA tools with in-depth information on Analog Layout concepts, techniques along with hands-on knowledge expected at fresher-level aspirants to the VLSI industry.

This course covers topics like CMOS process fabrication technology, understanding of components like MOS transistors, resistors and capacitors used in these technologies and the theory behind various layout techniques like shielding, common centroid matching, guard rings, ESD protection, etc.

Course Details

Duration:
Weekend: 12 weeks
Full Time: 6 Months Course + 6 Months Paid Internship

Training Delivery Model:

• Interactive Live Online Sessions.
• Lab access through VPN.

Certification:

GLS Certified Analog Layout Design Professional Course completion certificate to be awarded to all participants who successfully complete our tests and evaluation process.

Who can benefit from this Course:

• M.Tech / B.Tech Students.
• ACD engineers opting for a career in Layout.
• Working Professionals from the VLSI industry, currently working in other areas such as RTL Design, FPGA Design, Synthesis, STA, board-level testing, etc., and aspire to change to Analog Layout Design career.
• Faculties from Engineering Colleges across India.
• Professionals from Electrical and electronics engineering background with good academic Percentage but are working in other industries, and who are desiring to make a career in VLSI.
• Working professionals from Embedded background working in PCB designing, assembling, DSP, testing, RFIDs, etc.,

Pre-requisites:

● Working knowledge of Linux.
● Knowledge of Digital Electronics fundamentals.
● Knowledge of Verilog and the ability to design circuits using Verilog.
● Knowledge of CMOS Fundamentals and ASIC / SOC flow is an added advantage to understand the concepts.

Module 1 : Overview of Digital Design

  • Combinational & Sequential Logic
  • Flipflops, Latches & Counters
  • Memories

Module 2 : Fundamentals of Unix/Linux

  • Linux/Unix OS, Shell
  • Files & Directories
  • Few necessary commands

Module 3 : Semiconductors overview

  • Active & Passive devices
  • KCL & KVL
  • MOSFET Operations, few example circuits & 2nd order effects
  • CMOS basics, Fabrication Process
  • FinFET basics

Module 4 : Design for Manufacturability Checks

  • Antenna effect, Latch-up
  • Electro-migration, IR drop & Self-Heat
  • ERC & DRC

Module 5 : Challenges in Deep sub-micron process challenges

  • Well Proximity Effect (WPE), Length od Diffusion
  • Shallow Trench Isolation
  • Metal Density Effects

Module 6 : Analog Circuit Simulations

  • Introduction to Analog Design
  • CMOS Inverter design, parasitic extractions
  • Analyzing INV characteristics
  • Concepts of time delays

Module 7 : Layout Design Techniques

  • Common centroid & Interdigitation techniques
  • Critical signal shielding techniques
  • Constraint & module-based floor planning techniques
  • Guard rings

Module 8 : Custom Layout Techniques

  • Standard Cell layout design
  • I/O layout design
  • Memory Layout Design

Module 9 : Basic Analog Circuit Layout

  • Layout design & Physical verification of OPAMP, VCO, Band gap circuit and current mirror

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